Short-Random Request Absorbing Structure with Volatile DRAM Buffer and Nonvolatile NAND Flash Memory

This paper is to design a short-random request absorbing structure which can be constructed with volatile DRAM buffer and nonvolatile flash memory chips. Specifically, major weakness of NAND flash memory mostly comes from frequent short and random writes spreading in the whole logical address space, causing writing performance decrease. This phenomenon occurs because NAND flash memory does not allow in-place overwriting and some additional blocks are required for block updates. When short-random writes are frequently generated to use the limited number of update blocks, performance decreases significantly. Thus, a short-random absorbing DRAM buffer is designed to reduce such overhead. Especially the allocated blocks for update are divided into DRAM blocks and NAND chain-blocks according to the length of any writing request. Consequently it avoids several unnecessary erase operations and page copy operations. The trace based simulation result shows higher writing performance can be achieved in all sorts of traces, reducing block erase count with only 64Mbytes of DRAM writing buffer, where the overall erase count can be reduced by around from 24.35 percent to 8.08 percent compared to the SSD structure without any DRAM buffer. Thus, the proposed method can achieve scalable access performance, while minimizing the erase count and extending device lifetime. Key-Words: NAND flash memory, flash translation layer, disk buffer, DRAM, and solid state disk.